A. Field of the Invention
The present invention relates to a semiconductor device, and to a manufacturing method thereof.
B. Description of the Related Art
A vertical semiconductor element is such that current flows between an electrode provided on one main surface of a semiconductor substrate and an electrode provided on the main surface (the other main surface) on the side of the semiconductor substrate opposite to the one main surface. Because of this, in order to maintain a high breakdown voltage in the vertical semiconductor element, it is necessary to increase the thickness of a high resistance semiconductor layer existing between the electrodes. However, by increasing the thickness of the high resistance semiconductor layer existing between the electrodes, the on-state resistance increases. That is, there is a trade-off relationship between breakdown voltage and on-state resistance.
A semiconductor element with a super junction structure, wherein a pn-junction (a parallel pn-layer) in which an n-layer and a p-layer are repeatedly alternately disposed is formed in a drift layer, has been proposed as a way of improving the trade-off. The parallel pn-layer causes current to flow through the n-layer in an on-state, and withstands the breakdown voltage in an off-state by depleting the n-layer and p-layer. As a semiconductor element with a super junction structure is such that it is possible to increase the impurity concentration of the drift layer, it is possible to reduce the on-state resistance while maintaining a high breakdown voltage.
A method whereby embedding into a trench formed by selectively etching a semiconductor substrate is carried out by epitaxial growth has been proposed as a method of manufacturing a semiconductor element with a super junction structure. Also, a method whereby p-type and n-type buried regions cyclically formed in a depth direction by continuously carrying out ion implantation and epitaxial growth are thermally diffused and connected has been proposed as a simple method, with improved mass productivity, of manufacturing a semiconductor element with a super junction structure (for example, refer to Japanese Patent No. 3,988,262).
Reducing the on-state resistance by employing a super junction structure in a vertical semiconductor element is one means of increasing the added value of the vertical semiconductor element. Meanwhile, a semiconductor element called an intelligent switching device, wherein a lateral semiconductor element or some kind of passive element is formed on the same semiconductor substrate as the vertical semiconductor element, has been proposed as another means of increasing the added value of the vertical semiconductor element.
Heretofore, a drive circuit, control circuit, protection circuit, and the like, of a vertical semiconductor element used in an output stage have been configured of external, discrete parts. As opposed to this, an intelligent switching device is such that these circuits are configured of a lateral semiconductor element and various kinds of passive element formed on the same semiconductor substrate as the vertical semiconductor element used in the output stage.
In this way, an intelligent switching device is such that each kind of circuit element is formed on the same semiconductor substrate as the vertical semiconductor element used in the output stage, without using external, discrete parts. Because of this, it is possible to realize the heretofore known functions at a reduced size and lower cost. Element isolating technology whereby each element is electrically isolated is included as important technology for realizing an intelligent switching device.
When forming a plurality of semiconductor elements on the same semiconductor substrate, as in an intelligent switching device, element isolating technology is used in order not to cause a parasitic action between elements. For example, dielectric isolating technology, pn-junction isolating technology, self-isolating technology, and the like, are commonly known as element isolating technologies.
FIG. 31 is a sectional view showing a configuration of a main portion of a heretofore known intelligent switching device using dielectric isolating technology. As shown in FIG. 31, the heretofore known intelligent switching device using dielectric isolating technology is such that a vertical semiconductor element 511 and a lateral semiconductor element 512 are formed on an n− epitaxial layer 504. The lateral semiconductor element 512 configures a drive circuit, a control circuit, and a protection circuit.
The vertical semiconductor element 511 and lateral semiconductor element 512 are isolated from each other by a silicon oxide film 502, a trench isolating region 505 in which a silicon oxide film is embedded, and a high concentration n+ buried region 503, formed on an n+ substrate 501. The silicon oxide film 502 and high concentration n+ buried region 503 are formed between the n+ substrate 501 and n− epitaxial layer 504. The trench isolating region 505 penetrates the n− epitaxial layer 504 and high concentration n+ buried region 503, reaching the silicon oxide film 502. Element 509 is a p-well region of the vertical semiconductor element 511.
FIG. 32 is a sectional view showing a configuration of a main portion of a heretofore known intelligent switching device using pn-junction isolating technology. As shown in FIG. 32, the heretofore known intelligent switching device using pn-junction isolating technology is such that, in the same way as the intelligent switching device using dielectric isolating technology shown in FIG. 31, the vertical semiconductor element 511 and lateral semiconductor element 512 are integrated on the same substrate.
The vertical semiconductor element 511 and lateral semiconductor element 512 are isolated from each other by a p− layer 507 and high concentration p+ region 508 formed on the n+ substrate 501. The p− layer 507 is formed between the n+ substrate 501 and n− epitaxial layer 504. The high concentration p+ region 508 penetrates the n− epitaxial layer 504, coming into contact with the p− layer 507. Element 510 is a buried n+ region that penetrates the p− layer 507, coming into contact with the n− epitaxial layer 504 and n+ substrate 501.
FIG. 33 is a sectional view showing a configuration of a main portion of a heretofore known intelligent switching device using self-isolating technology. As shown in FIG. 33, the heretofore known intelligent switching device using self-isolating technology is such that, unlike the heretofore known intelligent switching device using pn-junction isolating technology shown in FIG. 32, the p− layer 507 and high concentration p+ region 508 are not provided. The separation of the vertical semiconductor element 511 and lateral semiconductor element 512 is done by increasing the gap between the elements. In FIG. 33, only a main portion of the element cross-sectional structure is shown, and the fact that the gap between the elements is greater than in the intelligent switching device shown in FIG. 32 is omitted from the drawing.
By configuring an intelligent switching device using the heretofore described element isolating technology in this way, there is realized an intelligent switching device wherein parasitic action between elements formed on the same semiconductor substrate is suppressed, and malfunction and breakage is prevented.
Also, a semiconductor element such that the trade-off between on-state resistance and breakdown voltage is improved using a super junction structure is described in Japanese Patent No. 3,988,262. Also, a semiconductor element configured of a super junction structure, and in which the cell pitch at which the n-layer and p-layer of the super junction structure are repeated is reduced, is described in JP-A-2007-012858.
Also, a lateral MOSFET such that low on-state resistance and high breakdown voltage are balanced using a multi-resurf structure is described in JP-A-2000-286417. The multi-resurf structure can be seen as a super junction structure. That is, the description in JP-A-2000-286417 is of a semiconductor device such that a high breakdown voltage lateral semiconductor element using a super junction structure and a lateral semiconductor element configuring a control circuit IC bounded by an isolating structure are formed on the same semiconductor substrate.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.